It can be appreciated that several trends presently exist in the electronics industry. Devices are continually getting smaller, faster and requiring less power, while simultaneously being able to support and perform a greater number of increasingly complex and sophisticated applications. One reason for these trends is an ever increasing demand for small, portable and multifunctional electronic devices. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. These devices rely on one or more small batteries as a power source while providing increased computational speed and storage capacity to store and process data, such as digital audio, digital video, contact information, database data and the like.
Accordingly, there is a continuing trend in the semiconductor industry to manufacture integrated circuits (ICs) with higher device densities. To achieve such high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers. To accomplish such high densities, smaller feature sizes, smaller separations between features and layers, and/or more precise feature shapes are required, such as metal interconnects or leads, for example. The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication processes by providing or ‘packing’ more circuits on a semiconductor die and/or more die per semiconductor wafer, for example.
One basic building block in semiconductor technology is the metal oxide semiconductor (MOS) transistor. MOS transistors are generally formed upon a semiconductor substrate 12, such as silicon, for example (FIG. 1). Such transistors 10 generally comprise source 14 and drain 16 regions formed within the semiconductor substrate 12, and a channel region 18 defined between the source 14 and drain 16 regions within the substrate 12. A gate structure or stack 20 is formed over the channel region 18, where the gate structure 20 comprises a gate dielectric or a thin layer of electrically insulating material 22 and a gate electrode or layer of electrically conductive material 24 overlying the gate dielectric 22. Sidewall spacers 26 reside on lateral edges of the gate structure 20 to facilitate the spacing of extension regions 28 associated with the source 14 and drain 16 regions. The sidewall spacers 26 also serve to protect the sidewalls of the gate structure 20. The channel region 18 has an associated length “L”, while the extent to which the transistor 10 extends transverse to the channel 18 is referred to as the transistor width “W”.
To activate the transistor 10, a bias (voltage) is applied to the gate electrode 24 to cause a current to flow within the channel 18. It can be appreciate that the amount of current developed for a given bias voltage is a function of the width-to-length ratio (W/L) of the transistor 10 as well as the mobility of carriers in the channel 18. For example, current can be more easily developed within the channel 18 when the carriers have a higher mobility. This allows for faster circuit operation and/or operations at lower bias voltages (to conserve power), for example. However, as dimensions are reduced to increase packing densities, the transistor width “W” and/or the channel length “L” are reduced. Reducing these dimensions can lead to various performance issues, such as slower transistor operations (e.g., reduced switching speeds, etc.).
Accordingly, a technique would be desirable that facilitates device scaling while promoting carrier mobility.